This invention relates to redundant computer systems with multiple processors and means for synchronizing the processors during each processor minor frame.
Redundant computer systems utilizing multiple, reconfigurable, processing modules are required and necessary in fault-tolerant control systems such as those used in digital flight control systems, for example. Where reconfigurable multiprocessor systems are utilized, synchronization is needed to force the operation of individual processors--and, more specifically, the start of each iteration or minor frame--to coincide in time. Such synchronization has previously been attempted at the computer clock level, and at the major frame level, i.e., the interval during which the processors execute their entire program.
The instant invention relates to an arrangement for synchronizing a multiprocessor system at the minor frame level (with a major frame being defined as an integral number of minor frames) by a combination of hardware and software.